CY62167GE18-55BVXI(Cypress Semiconductor Corp) 描述
Additional information about the CY62167GE18-55BVXI: CY62167G and CY62167GE are high-performance CMOS, low-power (MoBL ) SRAM devices with embedded ECC. Both devices are offered in single and dual chip enable options and in multiple pin configurations. The CY62167GE device includes an ERR pin that signals a single-bit error-detection and correction event during a read cycle. To access devices with a single chip enable input, assert the chip enable (CE) input LOW. To access dual chip enable devices, assert both chip enable inputs – CE1 as LOW and CE2 as HIGH. To perform data writes, assert the Write Enable (WE) input LOW, and provide the data and address on the device data pins (I/O0 through I/O15) and address pins (A0 through A19) respectively. The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs control byte writes and write data on the corresponding I/O lines to the memory location specified. BHE controls I/O8 through I/O15 and BLE controls I/O0 through I/O7. To perform data reads, assert the Output Enable (OE) input and provide the required address on the address lines. You can access read data on the I/O lines (I/O0 through I/O15). To perform byte accesses, assert the required byte enable signal (BHE or BLE) to read either the upper byte or the lower byte of data from the specified address location. All I/Os (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH for a single chip enable device and CE1 HIGH / CE2 LOW for a dual chip enable device), or the control signals are de-asserted (OE, BLE, BHE). These devices have a unique Byte Power-down feature where, if both the Byte Enables (BHE and BLE) are disabled, the devices seamlessly switch to the standby mode irrespective of the state of the chip enables, thereby saving power. On the CY62167GE devices, the detection and correction of a single-bit error in the accessed location is indicated by the assertion of the ERR output (ERR = High). See the Truth Table – CY62167G/CY62167GE on page 16 for a complete description of read and write modes. The CY62167G and CY62167GE devices are available in a Pb-free 48-pin TSOP I package and 48-ball VFBGA packages. The logic block diagrams are on page 2. The device in the 48-pin TSOP I package can also be configured to function as a 2M words × 8-bit device.